intel-gpu-hw-info

Intel GPU Hardware Specifications

Definitive reference for Intel GPU hardware across Xe2 and Xe3 architectures. All values sourced from kernel optimization work, profiling results, and verified benchmarks.

Version: 1.0.0 Last Updated: 2026-03-12

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Architecture Overview

• Xe2 is a GPU architecture used in multiple products:
  • Battlemage (BMG): Discrete GPU (dGPU), Intel Arc B-series
  • Lunar Lake (LNL): Integrated GPU (iGPU), Intel Core Ultra 200V series
• Xe3 is a GPU architecture used in:
  • Panther Lake (PTL): Integrated GPU (iGPU)
  • Panther Lake-H (PTLH): High-performance integrated GPU

All Xe2 and Xe3 products share the same ISA and programming model. Code is portable across dGPU and iGPU variants, though performance tuning differs significantly.

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Xe2 Architecture -- Battlemage (BMG) Discrete GPU

BMG Notes

• 32 XE cores x 8 EU x 8 threads = 2048 hardware threads total
• doubleGRF is mandatory for large tile GEMM/attention kernels (256 GRF entries per thread)
• Without doubleGRF, max WG threads is 64 but register pressure becomes the bottleneck
• Practical peak BW is ~520 GB/s; theoretical is ~550 GB/s
• L2 capacity is approximately 16 MB shared across all cores

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Xe2 Architecture -- Lunar Lake (LNL) Integrated GPU

LNL Notes

• Shared system memory means CPU activity impacts GPU bandwidth
• Fewer cores require careful workgroup sizing to avoid underutilization
• Same doubleGRF, SLM, and DPAS capabilities as BMG at the per-core level

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Xe3 Architecture -- Panther Lake (PTL) Integrated GPU

PTL Notes

• Only 12 XE cores means wave count is the dominant performance factor
• Concurrent WG capacity per core depends on threads per WG:
  • 32 threads/WG: 1 WG per core, 12 concurrent WGs total
  • 16 threads/WG: 2 WGs per core, 24 concurrent WGs total
  • 8 threads/WG: 4 WGs per core, 48 concurrent WGs total
• For recurrent (latency-bound) kernels, 8 threads/WG is optimal (fewer waves)
• For decode (throughput-bound) kernels at batch >= 4, 32 threads/WG is better
• Shared system RAM: budget approximately 1 GB for device buffers to avoid OOM
• Same ISA as BMG (Xe2), but different microarchitecture generation (Xe3)

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Xe3 Architecture -- Panther Lake-H (PTLH) Integrated GPU

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Architecture Comparison

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Roofline Parameters

BMG (32-core dGPU)

Peak FP16 XMX: 135 TFLOPS
Peak BW:       520 GB/s = 0.52 TB/s
Ridge Point:   135 / 0.52 = ~260 FLOPs/byte

• Kernels with arithmetic intensity (AI) < 260 are memory-bound
• Kernels with AI > 260 are compute-bound
• Most attention/GEMM kernels with HEAD_DIM >= 128 are compute-bound on BMG
• Practical peak BW is 520 GB/s; theoretical is 550 GB/s
• XVE FP32 (non-XMX): approximately 4 TFLOPS
• Kernel launch overhead: approximately 5-10 microseconds

PTL (12-core iGPU)

Peak FP16 XMX: 55 TFLOPS
Peak BW:       112 GB/s = 0.112 TB/s
Ridge Point:   55 / 0.112 = ~491 FLOPs/byte

• Higher ridge point means a wider memory-bound regime
• PTL's lower bandwidth makes more workloads memory-bound compared to BMG
• Shared memory with CPU means effective bandwidth varies with system load

Roofline Calculation Examples

GEMM: C[M,N] = A[M,K] x B[K,N]

FLOPs = 2 * M * N * K
Bytes  = (M*K + K*N + M*N) * sizeof(half)
AI     = FLOPs / Bytes

Flash Attention:

FLOPs = 4 * q_len * kv_len * head_dim * num_heads
      + 2 * q_len * kv_len * num_heads  (softmax)

Roofline Classification Thresholds

actual_ms > bw_limit_ms * 3.0  --> LATENCY BOUND (serial dependency or launch overhead)
actual_ms > bw_limit_ms * 1.5  --> PARTIALLY BW BOUND (stalls or contention)
actual_ms <= bw_limit_ms * 1.1 --> AT BW ROOFLINE

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DPAS/XMX Instruction Details (Xe2 and Xe3)

Instruction Format

xmx::dpas<SD, RC, T_dst, T_src0, T_src1, T_src2>(acc, src1, src2)

• SD = 8: Systolic depth (fixed for Xe2/Xe3)
• RC = 8: Repeat count
• T_dst, T_src0: Accumulator type (typically float)
• T_src1, T_src2: Input types (typically half or bfloat16)

Compute Per DPAS Call

• FP16: K = SD x 2 = 16 elements per systolic step
• BF16: K = SD x 2 = 16 elements per systolic step
• Output tile: M = RC rows x N = 16 cols per DPAS call

VNNI Layout Requirement

• B operand requires VNNI layout (interleaved 2-element packing)
• Use Transposed 2D load with uint32_t to get hardware VNNI transform
• VNNI packing: two FP16 values stored in one uint32_t, alternating across the K dimension

DPAS Pipeline Optimization

• Consecutive DPAS instructions without intervening sends/movs maximize XMX utilization
• Minimize XVE ALU operations inside DPAS loops (XVE + XMX parallelism lowers frequency)
• Use payload CSE: construct config_2d_mem_access once outside K-loop, only call set_x()/set_y() inside

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Memory Subsystem

Global Memory

• block_load: Contiguous 1D loads, up to 256 bytes per load for D32 (FP32)
  • block_load<float, 64> = 256 bytes (maximum for D32)
  • block_load<float, 128> = 512 bytes -- EXCEEDS LSC limit, must split to 2 x 64
  • block_load<half, 128> = 256 bytes (within limit)
• gather: Non-contiguous loads via scatter/gather
• lsc_load_2d: 2D block loads with hardware coalescing (preferred for tiled access)
• lsc_prefetch_2d: 2D prefetch (uses inline 6-argument form, not payload object)

SLM (Shared Local Memory)

• 64 KB per XE core, shared across all WGs on the same core
• 32 banks, 4 bytes per bank
• Bank conflict avoidance: pad SLM rows, ensure consecutive threads access consecutive banks
• slm_init(SLM_SIZE) must be the very first statement in the kernel

L3/LLC Cache

• BMG: approximately 8-16 MB, acts as implicit cache for global reads
• L2 capacity: approximately 16 MB shared across all cores
• Without cache busting, L2 can inflate bandwidth measurements by 2-3x

GRF (General Register File)

• 16 KB/thread in doubleGRF mode (256 registers x 64 bytes)
• Without doubleGRF: 128 registers x 64 bytes = 8 KB/thread
• doubleGRF is mandatory for large tile GEMM/attention kernels
• Not required for memory-bound kernels like GEMV (low GRF pressure)
• Register spill to stack memory kills performance -- always check compiler output

Cache Hints for Stores

• For lsc_block_store: L2 must be uncached or write_back -- NOT cached
• Valid store hints: (streaming, uncached), (write_through, uncached), (write_back, write_back)
• For loads: (streaming, cached) and (cached, cached) are both valid

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Key Differences: dGPU vs iGPU

Portability

• Same ISA and programming model -- code compiles and runs on both
• Same ESIMD intrinsics, DPAS instructions, SLM operations
• Performance tuning differs: iGPU needs smaller WG sizes, wave count optimization matters more
• Compile target differs: -device bmg vs -device ptl

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Thread Configuration Quick Reference

BMG (32 XE Cores)

32 cores x 8 EU/core x 8 threads/EU = 2048 HW threads
With doubleGRF: max 32 threads per WG
Design WG sizes so num_groups x local_size fills 2048 threads

PTL (12 XE Cores)

12 cores x 8 EU/core x 8 threads/EU = 768 HW threads
With doubleGRF: max 32 threads per WG

Threads/WG | EUs/WG | WGs/Core | Concurrent WGs (12 cores) | Waves for H=36
32         | 8      | 1        | 12                        | 3
16         | 4      | 2        | 24                        | 2
8          | 2      | 4        | 48                        | 1

LNL (8 XE Cores)

8 cores x 8 EU/core x 8 threads/EU = 512 HW threads

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Compilation Targets

# BMG (Xe2 dGPU)
icpx kernel.cpp -o kernel.exe -fsycl -fsycl-targets=spir64_gen \
  -Xs "-device bmg -options -doubleGRF"

# PTL (Xe3 iGPU)
icpx kernel.cpp -o kernel.exe -fsycl -fsycl-targets=spir64_gen \
  -Xs "-device ptl -options -doubleGRF"

• Do NOT use -fsycl-targets=intel_gpu_bmg_g21 (wrong target string)
• Do NOT use -O3 or -doubleGRF as top-level flags (they are ignored or warn)
• Check for spill warnings in compiler output: any spill > 0 indicates GRF pressure

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